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RM0008
Figure 232. I 2 C block diagram
Inter-integrated circuit (I 2 C) interface
DATA REGISTER
SDA
SCL
DATA
CONTROL
CLOCK
CONTROL
DATA SHIFT REGISTER
PEC CALCULATION
COMPARATOR
OWN ADDRESS REGISTER
DUAL ADDRESS REGISTER
PEC REGISTER
CLOCK CONTROL
REGISTER (CCR)
CONTROL REGISTERS
(CR1&CR2)
SMBALERT
STATUS REGISTERS
(SR1&SR2)
CONTROL
LOGIC
INTERRUPTS
DMA REQUESTS & ACK
Note: SMBALERT is an optional signal in SMBus mode. This signal is not applicable if
SMBus is disabled.
24.3.2
I 2 C slave mode
By default the I 2 C interface operates in Slave mode. To switch from default Slave mode to
Master mode a Start condition generation is needed.
The peripheral input clock must be programmed in the I2C_CR2 register in order to
generate correct timings. The peripheral input clock frequency must be at least:
●
●
2 MHz in Standard mode
4 MHz in Fast mode
As soon as a start condition is detected, the address is received from the SDA line and sent
to the shift register. Then it is compared with the address of the interface (OAR1) and with
OAR2 (if ENDUAL=1) or the General Call address (if ENGC = 1).
Note:
In 10-bit addressing mode, the comparison includes the header sequence (11110xx0),
where xx denotes the two most significant bits of the address.
Header or address not matched : the interface ignores it and waits for another Start
condition.
Doc ID 13902 Rev 9
627/995
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